Isolation of semiconductor devices is also required to minimize leakage currents, to suppress the latch-up with adjacent devices and for minimizing the die size of integrated circuits. Buried layers of dopants are another method of providing device isolation.
In U.S. Pat. No. 6,890,833 B2 one or more isolating trenches arranged in parallel and filled with a dielectric are disclosed. The trenches may have a depth of 600 nm e.g. and an aspect ratio of 6:1. For this type of trench a shallow-trench isolation (STI) can be considered.
Published U.S. patent application US2005/0179111 A1 discloses a CMOS device being isolated against the substrate and neighboured by a buried layer and by a DTI (deep trench isolation). The STI has a depth of typically 5 μm.
Such isolation is traditionally very important (although not limited) to HV devices such as HV transistors operating at Voltages higher than 5V and a power of >1W.
Traditionally HV (High Voltage) semiconductor manufacturing processes and HV transistors have either been developed without buried layers (called HV CMOS) or with buried layer (BCD . . . Bipolar CMOS DMOS). Currently there is no truly modular extension of a HV CMOS process towards a BCD process available.
Key requirement for such a modular extension is that LDMOS High Voltage transistors in the HV CMOS process can be operated also when they are surrounded by an optional buried layer (BL). E.g. for LDMOS (Lateral Double diffused MOS) devices, which have a reverse polarity capability below −50V in a lowly p-doped epitaxial layer, this requires a depth of >20 μm from the surface.
In order to contact the buried layer at such large depths a doped “deep sinker contact” is required. Reducing the isolation distance requires another trench that is deeper than the “deep sinker contact” trench.